IT Home July 4, 2026 — According to the latest paper posted on the Chinese Academy of Sciences scientific paper preprint platform ChinaXiv, He Tingbo, Head of Huawei Semiconductor, released the V2 version of "A Time Scaling Theory for Multi-Layer Electronic Systems" (also known as "Tao's Law" in the industry) on July 3.
Compared to the V1 version released on May 25, the new paper builds on the original theoretical framework with extensive engineering implementation details, quantitative measurement data, and product evolution roadmaps, further perfecting the post-Moore scaling theory system centered on the time constant τ.
In terms of paper structure, V2 consolidates the introductory sections of V1 into an 8-chapter complete discourse system with clearer logical layering.
V2 also adds multiple new schematic diagrams and physical images, covering the τ layered spatiotemporal model, LogicFolding architecture, bonding interface cross-sections, Unified Bus interconnect architecture, Hi-ONE optical engine, and other core technologies.
On engineering implementation, V2 deeply elaborates the gear ratio concept of the core technology LogicFolding. When the hybrid bonding pitch approaches the top metal routing dimension, the 3D design space shifts from traditional "macro-block-level discrete optimization" to "unit-level continuous optimization," enabling globally optimal vertical logic partitioning and breaking through the limitation of traditional 3D stacking that only allows partitioning by functional blocks.
V2 also adds mass-production measurement data tables, clearly presenting voltage, frequency, normalized power consumption, area, and power density parameters for Kirin 2026 compared to the baseline Kirin 9030 Pro.
V2 also refines the full-scenario roadmap, clarifying technology evolution milestones. On the mobile side, it adds evolutionary paths such as TSV downward migration from the top metal to the M6 layer and multi-active-layer stacking. On the AI side, it specifies the iteration cadence for the Ascend series accelerators.
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A Time Scaling Theory for Multi-Layer Electronic Systems
Author:Tingbo He1
Affiliation:1. Huawei
Submitted:2026-07-03 09:16:50
Abstract:For six decades, Moore's geometric scaling drove progress in semiconductors. That industry compact no longer holds: returns from pure dimensional shrinking have flattened, leading-edge design budgets exceed one billion dollars per chip, and cost-per-transistor at the most advanced nodes is no longer falling. This perspective argues for a successor scaling principle — τ scaling — that adopts time itself, rather than transistor area, as the primary metric of progress, applying a single characteristic time constant τ as the unifying optimization target across twelve orders of magnitude, from a switching transistor to a data-center workload. Two production-scale demonstrations are presented. On a mobile SoC, LogicFolding — a methodology that partitions digital, analog, and memory circuits across vertically stacked active tiers — delivers a 55% step-wise increase in transistor density and a 41% power-efficiency gain at a fixed device node. On AI systems, a co-designed stack comprising the memory-semantic Unified Bus fabric, near-packaged Hi-ONE optical I/O, and edge-to-surface 3D Folding projects more than 100× growth in hardware integration by 2035. The deeper claim is methodological: τ scaling is the first scaling principle since Dennard to establish a shared optimization target across the entire computing stack.
Keywords:
From:He Tingbo
Journal:Science China
Submission Status:Accepted by Journal
Citation:ChinaXiv:202605.00224 (or this version ChinaXiv:202605.00224V2)
DOI:10.12074/202605.00224
CSTR:32003.36.ChinaXiv.202605.00224
DOI:10.12074/202605.00224
CSTR:32003.36.ChinaXiv.202605.00224
ScienceChain TXID:8ad236f3-2ebb-4d8f-aabc-fe09198d12b5
Recommended Citation:Tingbo He. A Time Scaling Theory for Multi-Layer Electronic Systems. Chinese Academy of Sciences Scientific Paper Preprint Platform. [DOI:10.12074/202605.00224] (Click to copy)
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